Staff R&D Engineer (Location:- Bangalore/ Noida)

Job Description:-

The candidate will be joining for the Magellan R&D team in India. The ideal candidate will be the one you can technically lead the team, and do technical development as an individual contributor.

Magellan™ is a hybrid RTL formal verification product that allows engineers to find deep, corner-case bugs, quickly, resulting in shortened functional verification cycles and high-quality designs. Magellan’s unique hybrid architecture combines the strengths of new, advanced formal engines with the strengths of a built-in VCS® simulation engine to verify properties on large and complex designs.

The candidate Technically leads & delivers multi-project functionality in each product release. Drives the initiative visibly within the group and is recognized as the leader and owner of the initiative. Sells the vision to peers and upper management. Works hands-on and implements software for the functional area.

Accountable for quality of work, results obtained and productivity of the employee's supervised. Develops project schedules and executes w/o direction from manager. Assigns tasks to the team and tracks progress towards completion.  Effectively prioritizes work and trades off project milestones vs. features.

Assignments are given by manager in terms of broad objectives and strategy. Identifies problems, solutions and resources needed to meet the objectives. Responsible for getting the final solution to problems. Problems may be new and very open ended. Runs effective meetings needed to work through problems, and also helps the team get over (or around) 'brick walls' that they run into. Demonstrates excellent decision making in selecting and discarding technology alternatives. Frequently works with R&D/CAE/AC/Marketing managers/directors. Works closely with global cross-functional teams in defining, implementing and delivering the solutions.

Develops vision of future customer requirements and needs. Acts as customer advocate and judge of user impact. Collaborates and plans effectively with customers in strategic partnerships. Establishes customer relationships or academic contacts.

-   Typically requires a BS/MS in CS/EC with 10+ years of relevant experience.

-   Excellent coder in C/C++.

-   Strong background in algorithms and data structures

-   Prior knowledge/experience/education in ‘Formal Technologies’ (model checking, LTL, CTL, formal engines like BDD, SAT) is required.

-   Prior knowledge/experience/education in ‘Logic Simulation’ is required.

-   Prior Knowledge of digital logic is required.

-   Excellent analytical, logical reasoning and problem-solving skills

-   Prior experience in EDA optimization algorithms is beneficial.

-   Familiar with software development process, debugging tools and configuration management tools.

-   Should have experience working in a multi-person product development environment with high dependencies and tight schedules.

-   Receives little to no instructions on day-to-day work, general instructions on new assignments and projects.

-   Resolves a wide range of issues in creative ways. Exercises judgment in selecting methods and techniques to obtain solutions.

It is essential that the candidate has high integrity and a positive attitude. He/She will be a highly motivated, responsible, and dependable individual with self-drive and demonstrate a strong desire to learn and explore new technologies. It is essential that the individual has fast learning abilities. Initiative is required to drive solutions to problems when working in a team. He/She will be flexible to work on multiple tasks based on project priorities. The individual will be an excellent team player and is expected to have good oral and written communication skills and proficiency in English language.

Please drop me an email at vishalka@synopsys.com if interested. 

R&D Engineer, II (Layout:- Std Cell IP development)

JOB RESPONSIBILITIES:

• Be responsible for layouts, simulations, netlist extraction, as required in Std Cell IP development
• Be involved in all phases of Std Cell IP development, including project planning, problem identification, design specification, development, verification and product support
• Design and implement scripts required to automate parts of the Std. Cell IP development flow
• Exercise judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results
• Develop state of the art solutions through technical contributions, that lead to significant product differentiation

REQUIRED QUALIFICATIONS:

• B.Tech/M.Tech degree in Electonics Engineering or an appropriate engineering area, with excellence and consistency in academic records.
• Atleast 2 years of related experience in layouts, netlist extraction at cell level and at design level for Standard Cell IP development with deep understanding of technical challenges involved in design of Std Cell Libraries and their application. Candidates with prior experience in working on the latest technology nodes will be preferred. Fresh M. Tech graduates will also be considered for this position
• Excellent analytical, logical reasoning and problem-solving skills
• Good knowledge of electrical circuit analysis and design and CMOS fundamentals
• Good understanding of digital electronics
• Knowledge of CDBA/OA and writing/debugging skill code
• Exposure to any programming or scripting language and UNIX/Linux OS
• Knowledge of Timing/Power/Noise characterization methodologies and exposure to any characterization tool will be an added advantage
• Knowledge of behavioral/timing/power EDA models, like Verilog, VHDL, Liberty etc. will be an added advantage
• Prior knowledge and experience of EDA tools/Std. Cell IP development flow/Physical design flow will be a big plus
It is essential that the candidate has high integrity and a positive attitude. He/She will be a highly motivated, responsible, and dependable individual with self-drive and demonstrate a strong desire to learn and explore new technologies. It is essential that the individual has fast learning abilities. Initiative is required to drive solutions to problems when working in a team. He/She will be flexible to work on multiple tasks. The individual will be an excellent team player and is expected to have good oral and written communication skills and proficiency in English language.


Please forward your resume to vishalka@synopsys.com if interested.

R&D Engineer, Sr I:- Verification IP (Bangalore)

Must:

1) 5+ years of experience in Functional Verification

2) 3+ years of experience with System Verilog

3) 1+ years of experience with OVM/UVM/VMM 

4) Have worked once in all phases of function verifications i.e. verification planning, architecture, BFM design and implementation, sequence implementation, test case, functional coverage etc.

5) Have worked in any of high speed serial I/F and have deep understanding. i.e. MIPI, HDMI, SATA, USB, PCI Express etc.

6) Know one of the scripting language(Perl/Shell/tcl/awk etc).

Optional:

1) Good understanding of Verilog/VHDL RTL

2) Have fair understanding of system level verification and can suggest new ideas for effective verification.

Please drop me an email at vishalka@synopsys.com if interested.

R&D Engineer, Sr II (Senior Circuit Design Engineer)

JOB RESPONSIBILITIES:

+ Be responsible for circuit design, schematics, layouts, simulations, netlist extraction, LEF and related EDA models as required in Std Cell IP development

+ Be involved in all phases of Std Cell IP development, including project planning, problem identification, design specification, development, verification and product support

+ Design and implement scripts required to automate parts of the Std. Cell IP development flow

+ Exercise judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results

+ Develop state of the art solutions through technical contributions, that lead to significant product differentiation



REQUIRED QUALIFICATIONS:

+ B.Tech/M.Tech degree in Electronics Engineering, with excellence and consistency in academic records.
+ At least 8+ years of related experience in circuit design (schematic simulations, layouts, netlist extraction) at cell level and at design level for Standard Cell IP development with deep understanding of technical challenges involved in design of Std Cell Libraries and their application. Candidates with prior experience in working on the latest technology nodes will be preferred.
+ Expertise in CDBA/OA and writing/debugging skill code
+ Excellent analytical, logical reasoning and problem-solving skills
+ Excellent knowledge of electrical circuit analysis and design and CMOS fundamentals
+ Excellent understanding of digital electronics
+ Exposure to any programming or scripting language and UNIX/Linux OS
+ Knowledge of Timing/Power/Noise characterization methodologies and exposure to any characterization tool will be an added advantage
+ Knowledge of behavioral/timing/power EDA models, like Verilog, VHDL, Liberty etc. will be an added advantage
+ Prior knowledge and experience of EDA tools/Std. Cell IP development flow/Physical design flow will be a big plus

It is essential that the candidate has high integrity and a positive attitude. He/She will be a highly motivated, responsible, and dependable individual with self-drive and demonstrate a strong desire to learn and explore new
technologies. It is essential that the individual has fast learning abilities. Initiative is required to drive solutions to problems when working in a team. He/She will be flexible to work on multiple tasks. The individual will be an excellent team player and is expected to have good oral and written communication skills and proficiency in English language.
Please drop me an email at vishalka@synopsys.com if interested. 

R&D Engineer, II (Standard Cell IP development)

Job Description:-


+ Be responsible for circuit design, schematics, layouts, simulations, netlist extraction, LEF and related EDA models as required in Std Cell IP development

+ Responsible for physical design, development and verification of Standard Cells in various deep sub-micron technologies.

+ Design and implement scripts required to automate parts of the Std. Cell IP development flow

+ Be involved in all phases of Std Cell IP development, including project planning, problem identification, design specification, development, testing and product support

+ Exercise judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results

+ Develop state of the art solutions through technical contributions that lead to significant product differentiation

+ Sound understanding of various high performances, low power design techniques

+ Sound understanding of all the ASIC methodologies, flows.


REQUIRED QUALIFICATIONS:

+ B.Tech/M.Tech degree in Electonics Engineering, with excellence and consistency in academic records.

+ At least 3 years of related experience in circuit design and layouts for Standard Cell IP development

+ Excellent analytical, logical reasoning and problem-solving skills

+ Strong understanding of electrical circuit analysis and design and CMOS fundamentals

+ Strong understanding of digital electronics

+ Exposure to any programming or scripting language and UNIX/Linux OS

+ Knowledge of Timing/Power/Noise characterization methodologies, ECSM, CCS, NLDM models and working experience with any characterization tool, behavioral/timing/power EDA models, like Verilog, VHDL, Liberty, Physical design flow will be an added advantage


It is essential that the candidate has high integrity and a positive attitude. He/She will be a highly motivated, responsible, and dependable individual with self-drive and demonstrate a strong desire to learn and explore new technologies. It is essential that the individual has fast learning abilities. Initiative is required to drive solutions to problems when working in a team. He/She will be flexible to work on multiple tasks. The individual will be an excellent team player and is expected to have good oral and written communication skills and proficiency in English language.

Please drop me an email at vishalka@synopsys.com if interested.

R&D Engineer, Sr 1 (Circuit Design Engineer)

Job Description and Requirements:-


Qualification:


Experience Required: 6+ yearsEducation: Btech/Mtech/Phd. Electronics/Electrical engineering


Skills/Experience:


- Recent experience delivering DDR I/O designs for low power wireless devices.- Solid understanding of related CMOS process technology issues in 28nm and smaller.- I/O design methodology & flow, Calibration, JTAG design requirements, understanding of analog circuitry, familiarity with basic ESD concepts.- Familiarity with ASIC flow: Synopsys libraries, LEF generation, Place & Route & understanding of top level verification flow.- DDR2/DDR3 design experience including LPDDR/LPDDR2.- General Understanding of the DDR Timing, ODT and SDRAM functionality.- Familiarity with: JEDEC requirements for DDR interfaces & standards; Power & Signal Integrity.- Additional preferred experience in design and development of GPIO's, Special high speed IO's such as LVDS, USB, MIPI, DigRf, PLL's, ADC, etc- Ability to foster accountability and ownership through hands-on technical leadership.- Excellent written and verbal communication skills in interactions with customers, and internal development teams.- 5+ year's CMOS IO circuit development expertise


Responsibilities:


- DDR/DDR2/DDR3/LPDDR/LPDDR2 I/O Circuit and layout design including GPIO and Special IO’s.- Provide subject matter expertise and technical leadership in design of high speed I/Os such as DDR.- Work with DDR PHY team, package engineers and system engineers to meet design specifications.


Interested candidates can forward their resumes to vishalka@synopsys.com

Intern (Technical)

1. Job Description: The focus of work would be in one of the following areas:USB2/USB3/Ethernet

The nature of work would be on the following lines:
Architecture exploration of the sub-blocks within one of these IPs to optimize for area, speed and power
VLSI Design & verification of these sub-blocks/exploration of latest features and standards

Requirements:

HDL Languages coding experience preferably in Verilog/Vera/System Verilog is preferable.
The candidate must have completed Bachelors degree in electronics/ Electrical engg. Partial completion of MS/MTech preferable

2. Job Description:- This Engineer will work with the Design Compiler R&D team to implement synthesis product capabilities including but not limited to Synthesis for Multi-Voltage design, usability and infrastructure enhancements. The engineer will also have to support existing functionality and strive to improve the quality  and maintainability of the software. Development will be in C. The engineer will require to perform first level debugging on any issues hit during development, using standard tools available in-house. As part of the job, the engineer will also design and develop testcases in VHDL/Verilog to test the features/bugs fixed by the individual. The engineer will also be responsible to validate the code changes across the existing Regression testing system and QoR suite. The engineer will have to adhere by the standard practices followed such as code review, testing the code through purify, testing across multiple platforms etc.

Requirements:

Graduate/Post graduate student in CS/EC with excellent C programming skills, thorough in Data Structures and Algorithms and good Digitial Design knowledge.

Knowledge of PERL, Tcl and Shell scripting; debugger(gdb); HDLs like VHDL/Verilog are an added advantage.

Should be a self learner, committed, good team player with good written/oral communication skills.

We are looking for Interns with Good Academic background. Please email me your resume at vishalka@synopsys.com